1. Field of the Invention
The present invention relates to an art for improving a quality and a reliability of a semiconductor device, and particularly, the present invention relates to an art for improving a quality and a reliability of a semiconductor device by improving a decay durability in the vicinity of a wiring to be installed in an interlayer-insulator-film formed by stacking a plurality of insulator films including a low-relative-dielectric-constant-film.
2. Description of the Related Art
In recent years, for speed-up of a semiconductor device including an LSI, lowering of wiring resistance and lowering of relative dielectric constant of an interlayer-insulator-film or the like have been promoted. Specifically, a material of wiring is changed from aluminum (Al) into copper (Cu). In addition, as an interlayer-insulator-film, a low-relative-dielectric-constant-film (a low-k film) is also changed from a simple SiO2 film into a SiO2 film having fluorine doped thereon, and a SiO2 film containing an organic constituent.
The low-relative-dielectric-constant-film is formed by lowering a density of a material or eliminating a polarity of the material or the like. For example, in order to lower the density of the material, generally, the material is made porous. Thus, since the low-relative-dielectric-constant-film has a low film density, generally, the low-relative-dielectric-constant-film has a low mechanical property value such as a Young's modulus or the like. In other words, the low-relative-dielectric-constant-film has a low strength of the material itself. In addition, the low-relative-dielectric-constant-film has a film structure with low polarity for lowering the dielectric constant in the film. Therefore, an adhesive strength on a stacking boundary face in a stacked insulator film formed by stacking the low-relative-dielectric-constant-film with each other or stacking the low-relative-dielectric-constant-film and other film is low. Specifically, a material of a film changes its nature depending on saturation of gas that is used on machining and forming a via hole and a groove for a wiring or the like on the low-relative-dielectric-constant-film and a machining process. Thereby, there is concern that the mechanical strength of the material itself of the low-relative-dielectric-constant-film may be lowered, or the adhesive strength on the boundary face in the stacked insulator film including the low-relative-dielectric-constant-film may be lowered.
A shortage of a strength caused by a weakness of the film strength of this low-relative-dielectric-constant-film is a serious obstacle and particularly, this shortage of the strength becomes a factor of lowering a quality, a reliability, a performance or the like of the entire semiconductor device in a multi-layer process to form a multi-layer structure of the wiring in the interlayer-insulator-film formed by the stacked insulator film including the low-relative-dielectric-constant-film. For example, as one main failure caused by a weakness of the film strength of the low-relative-dielectric-constant-film, separation of an insulator film boundary face in a CMP step may be considered. Specifically, in the case that a region made only of an insulator film having no wiring spreads widely to some extents, separation of a boundary face will easily occur in the interlayer-insulator-film due to a stress generated by a friction between a polishing pad and a surface of a wafer in performing CMP. Therefore, in order to prevent such a separation of a boundary face, an art for introducing a reinforcement member having a high strength such as a metal in the region made only of an insulator film having no wiring has been suggested. For example, in Jpn. Pat. Appln. KOKAI Publication No. 2005-150389, an art for arranging a dummy wiring, a dummy plug or the like that does not configure an actual energizing path in the low-relative-dielectric-constant-film has been suggested. Thereby, by easing a stress that is generated by a friction between surfaces of the polish pad and the wafer in performing CMP and is applied to the interlayer-insulator-film, a quality, reliability, performance or the like of the entire semiconductor device are intended to be improved.
An effect of easing the stress on the CMP step by this dummy wiring depends not only on a coverage of the dummy wiring but also on a size of the dummy wiring. However, in practice, an art for optimizing the size of the dummy wiring has not been substantially studied yet. Therefore, a stress lowering effect due to the dummy wiring has not been fully achieved, so that a concern that the boundary face is separated in the CMP has not been completely solved yet. In addition, in designing of the dummy wiring, a designing method in consideration of a mechanical property value of the interlayer-insulator-film employing the low-relative-dielectric-constant-film has not been used. Therefore, every time a generation of the semiconductor device and the design rule thereof is changed or a type of the interlayer-insulator-film is changed, it is necessary to decide a dummy wiring structure in which the boundary face is hardly separated by a trial and an error while expending large amounts of masks and lots. As a result, until a desired dummy wiring structure is obtained, many steps, much manpower, much time, and much cost have been expended. Then, even in the case that optimization of the size of the dummy wiring in consideration of a mechanical property value of the interlayer-insulator-film including the low-relative-dielectric-constant-film is not carried out, there was high possibility that a defect of the device is generated due to the boundary face separation in the CMP.
Thus, according to a conventional dummy wiring art, a crucial failure is easily generated in the semiconductor device and the manufacturing method thereof. In other words, a quality, reliability, a performance or the like of the semiconductor device is lowered and the defective semiconductor device is easily manufactured. As a result, a manufacturing yield of the semiconductor device is lowered and a manufacturing efficiency of the semiconductor device is easily lowered. Further, a manufacturing cost of the semiconductor device is difficult to control.